Multi-Level Fault Injection Methodology Using UVM-SystemC

The growing complexity of SoCs requires more accurate and faster test and verification in the early stages of the design. Fault injection plays an important role in ensuring safety, security, and fault-tolerance system specifications are met at various stages of the design. The SystemC language standard provides the possibility of system-level design modeling and early evaluation in the design flow. In this paper, we propose a simulation-based multi-level fault injection framework in SystemC. Our framework makes use of Universal Verification Methodology (UVM), a well-known language independent standard developed to unify the verification flow, to systematize the use and reuse of the test sequences for different test scenarios. To evaluate our framework, we study the impact of faults on a RISCV-like processor described in three levels of abstraction (ISS, RTL, and Gate-level) for both permanent and transient faults.