Design Specification and Simulations of a Miller compensated Operational Amplifier with 75dB Gain
Muhammad Ahmad, Sohail Ahmad, Arshad Hussain, Zeeshan Akbar
Abstract
Open-access reader
Muhammad Ahmad, Sohail Ahmad, Arshad Hussain, Zeeshan Akbar
Abstract
Open-access reader
This paper presents a two-stage Miller compensated operational amplifier design using cadence 55nm CMOS technology. This circuit provides a single ended output due to mirror pole is implemented while the input of this operational amplifier is differential. A biasing circuit is also designed and attached with this amplifier. This operational amplifier provides a gain of 75.41dB while the phase margin is off 70o. The Gain bandwidth of this operational amplifier is 9.5MHz. The power consumption of this overall circuit including the biasing circuit is 154.69µW. The other performance parameters are also analyzed and provide in this paper. The mathematical calculation for the circuits is also presented. Due to medium power consumption and higher gain bandwidth this amplifier can be used in different data converters like Delta-Sigma ADC. Because the performance of this ADC is depending upon the higher Gain Bandwidth.
OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
This paper presents a two-stage Miller compensated operational amplifier design using cadence 55nm CMOS technology. This circuit provides a single ended output due to mirror pole is implemented while the input of this operational amplifier is differential. A biasing circuit is also designed and attached with this amplifier. This operational amplifier provides a gain of 75.41dB while the phase margin is off 70o. The Gain bandwidth of this operational amplifier is 9.5MHz. The power consumption of this overall circuit including the biasing circuit is 154.69µW. The other performance parameters are also analyzed and provide in this paper. The mathematical calculation for the circuits is also presented. Due to medium power consumption and higher gain bandwidth this amplifier can be used in different data converters like Delta-Sigma ADC. Because the performance of this ADC is depending upon the higher Gain Bandwidth.
Key concepts: Fully differential amplifier, Operational amplifier, Phase margin, Open-loop gain, Direct-coupled amplifier, Operational transconductance amplifier, Current-feedback operational amplifier, Gain–bandwidth product