Comparative Analysis of Phase/Frequency Detector in a Complete PLL System

In many integrated radio frequency (RF) transceivers, the phase-locked loop (PLL) serves as a frequency synthesizer. This work goes to test various different phase/frequency detector blocks with a standard charge pump and Voltage controlled oscillator design. These include the comparison of different phase-frequency detectors (PFD) based upon D-flipflops, latches (Latch PFD) & pass transistors (PTPFD) to the more complex Pre-charged PFD. The best results of the PFDs in the PLL system in order are Pre-charge PFD, PT-PFD, Latch PFD and D-flipflop PFD. A charge pump PLL (CPLL) with a frequency range of [80 MHz -800 MHz] is simulated using Cadence Virtuoso (Spectre) at 180nm technology (scl\_pdk) with 1.8 V supply voltage. The phase noise of the VCO is less than -50dBc/Hz at 10MHz and is closer to 110dBc/Hz at 1GHz.