Simulation and Comparative Analysis of Dynamic Comparators at 1MHz for Biomedical Applications

SAR ADC is one of the most demanding Analog to digital converter for medium speed, medium resolution applications like ECG, EEG, and related biomedical applications. In this paper we have designed and simulated the dynamic comparators with noise rejection and amplification capability in CADENCE Virtuoso 45 nm technology node. Designed Comparators are simulated at 0.8V and various parameters like power dissipation, maximum operating frequency, delay and offset voltage are compared. Designed comparators are well employable in SAR ADC with maximum operating frequency of 1MS/s. comparators are operated at varying supply voltage from 0 to 1 V. Basic comparator dissipates 9.17 pW as static power and 520.2 nW as dynamic power at VDD of 1 V and INN, INP difference of 0.9 V. Compared to basic comparator, dynamic comparator with tail transistors can be operated at 0.5 V with static power of 4.143 pW and 3.720 nW as dynamic power dissipation. Operating frequency of designed comparators is of 1 MHz with propagation delay of 522 ns by dynamic comparator with tail transistors and 480 ns as of basic comparator.