Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition
Shucheng Yang, Xiaoping Gao, Jie Ren
Abstract
Shucheng Yang, Xiaoping Gao, Jie Ren
Abstract
Rapid single flux quantum (RSFQ) logic is a promising technology to supersede CMOS logic in some specialized areas due to providing ultrafast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially, for nonlinear sequential blocks with feedback loops. Thus, this article presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.
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Rapid single flux quantum (RSFQ) logic is a promising technology to supersede CMOS logic in some specialized areas due to providing ultrafast and energy-efficient circuits. To realize a large-scale integration design, electronic design automation (EDA) tools specialized for RSFQ logic are required due to the divergences in logic type, timing constraints, and circuit structure compared with CMOS logic. Logic synthesis is crucial in converting behavioral circuit description into a circuit netlist, typically combining combinational and sequential circuit synthesis. For the RSFQ logic, the sequential circuit synthesis is challenging, especially, for nonlinear sequential blocks with feedback loops. Thus, this article presents a sequential circuit synthesis algorithm based on finite state machine (FSM) decomposition, which ensures design functionality, lowers costs, and improves the RSFQ circuit performance. Additionally, we present the synthesis processes of the feedback logic and the 2-bit counter to demonstrate how the proposed algorithm operates, and ISCAS89 benchmark circuits reveal our method’s ability to synthesize large-scale sequential circuits.
Key concepts: Sequential logic, Logic optimization, Register-transfer level, Asynchronous circuit, Computer science, Netlist, Logic synthesis, Logic gate