A 2.5 GS/s, 7-bit time-interleaved SAR ADC with real-time data output

This letter presents the design and measurement results of a 2.5 GS/s 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) with real-time data output via the JESD204B protocol using two lanes at 12.5 Gb/s each. The ADC is implemented in a 22-nm fully-depleted silicon-on-insulator (FDSOI) technology and consists of four time interleaved ADC cores. It consumes 43 mW overall, while the analog frontend including the four ADC cores and the interleaver consumes only 7.8 mW. In the first Nyquist zone, the effective number of bits (ENOB) is larger than 6.1 bit leading to a Walden Figure-of-Merit (FOM_W) of 45 fJ/conv.-step and a Schreier Figure-of-Merit (FOM_S) of 150.5 dB. Integral (INL) and differential nonlinearity (DNL) are both well below 0.5 LSB for all measurement scenarios.