Design and Simulation of a Low PDP Full Adder by Combining Majority Function and TGDI Technique in CNTFET Technology

In this study, a full adder based on the transmission gate diffusion input (TGDI) technique and majority function is presented in carbon nanotube field-effect transistor (CNTFET) technology. The proposed design consists of 18 transistors and is simulated using HSPICE software at a voltage of 0.8 V, a frequency of500 MHz, and a load capacitance of 1 fF in 32 nm technology. The simulation results show the reasonable performance of the sum and carry output signals as well as the improvement in power consumption, latency, power-delay product (PDP), and energy-delay product (EDP). The power consumption and delay of the proposed design are, respectively, 697 nW and 13.8 ps, which result in a PDP of 9.67 fJ and an EDP of 1.34 $\times 10^{-28}$ Js.