Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing\n Margins

This paper summarizes the idea of Adaptive-Latency DRAM (AL-DRAM), which was\npublished in HPCA 2015, and examines the work's significance and future\npotential. AL-DRAM is a mechanism that optimizes DRAM latency based on the DRAM\nmodule and the operating temperature, by exploiting the extra margin that is\nbuilt into the DRAM timing parameters. DRAM manufacturers provide a large\nmargin for the timing parameters as a provision against two worst-case\nscenarios. First, due to process variation, some outlier DRAM chips are much\nslower than others. Second, chips become slower at higher temperatures. The\ntiming parameter margin ensures that the slow outlier chips operate reliably at\nthe worst-case temperature, and hence leads to a high access latency.\n Using an FPGA-based DRAM testing platform, our work first characterizes the\nextra margin for 115 DRAM modules from three major manufacturers. The\nexperimental results demonstrate that it is possible to reduce four of the most\ncritical timing parameters by a minimum/maximum of 17.3%/54.8% at 55C while\nmaintaining reliable operation. AL-DRAM uses these observations to adaptively\nselect reliable DRAM timing parameters for each DRAM module based on the\nmodule's current operating conditions. AL-DRAM does not require any changes to\nthe DRAM chip or its interface; it only requires multiple different timing\nparameters to be specified and supported by the memory controller. Our real\nsystem evaluations show that AL-DRAM improves the performance of\nmemory-intensive workloads by an average of 14% without introducing any errors.\nOur characterization and proposed techniques have inspired several other works\non analyzing and/or exploiting different sources of latency and performance\nvariation within DRAM chips.\n