2022Journal of Physics Conference SeriesOpen access

High-fidelity circuit simulation of AQFP circuits through compact models extracted from layout

Coenrad J. Fourie, Kyle Jackman

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Abstract

Abstract Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit designers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout. Hand-designed netlists mostly do not contain all the mutual inductances between inductors. The lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph and all inductors should be coupled. In this paper, we show that full-circuit inductance extraction of AQFP layout where self and mutual inductances are specified by the designer produces small but possibly significant errors due to mismatch between the design schematic and the layout. With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout. We propose compact model extraction as the final step in cell library characterisation.

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Abstract Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit designers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout. Hand-designed netlists mostly do not contain all the mutual inductances between inductors. The lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph and all inductors should be coupled. In this paper, we show that full-circuit inductance extraction of AQFP layout where self and mutual inductances are specified by the designer produces small but possibly significant errors due to mismatch between the design schematic and the layout. With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout. We propose compact model extraction as the final step in cell library characterisation.

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Available abstract

Abstract Adiabatic Quantum Flux Parametron (AQFP) superconductor logic circuits rely on magnetic coupling between the gate and clock and control lines to function. Circuit designers start by designing a circuit netlist, selecting parameters to fit design objectives, optimizing the netlist in simulation and then progressing to integrated circuit layout. Hand-designed netlists mostly do not contain all the mutual inductances between inductors. The lack of a complete set of mutual inductances can limit the accuracy of the designed netlist. For a circuit netlist to be an exact representation of the layout, the number of inductors should be equal to the number of fundamental cycles in the netlist graph and all inductors should be coupled. In this paper, we show that full-circuit inductance extraction of AQFP layout where self and mutual inductances are specified by the designer produces small but possibly significant errors due to mismatch between the design schematic and the layout. With compact simulation model extraction, which we added to the InductEx tool chain, a much more accurate simulation model that includes all mutual inductances can be obtained to verify circuit performance after layout. We propose compact model extraction as the final step in cell library characterisation.

Key concepts: Netlist, Circuit extraction, Integrated circuit layout, Inductance, Electronic engineering, Computer science, Design layout record, Physical design

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