2022•Unpublished venueRequires access

Exploiting Scheduling Information for Efficient High-Level Synthesis Design Space Exploration

Xingyue Qian, Jian Shi, Shi Li, H. Zhang, Lijian Bian, Weikang Qian

Abstract

High-level synthesis (HLS) automatically transforms highlevel programming language into RTL design. It is widely used to program FPGAs as accelerators. HLS tools have many knobs that can be controlled by users to produce designs with different area-latency trade-offs.

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Key concepts: High-level synthesis, Computer science, Design space exploration, Field-programmable gate array, Computer architecture, Scheduling (production processes), High-level programming language, Latency (audio)