L. Pfennings, W. Mol, J. Bastiaens, J. van Dijk
Abstract
This paper will discuss subnanosecond gate delays (0.8ns) obtained for complex logic gates designed with cascode-coupled NMOS-PMOS loads, differential logic NMOS trees, and interconnect lines with 2.4V swings.
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This paper will discuss subnanosecond gate delays (0.8ns) obtained for complex logic gates designed with cascode-coupled NMOS-PMOS loads, differential logic NMOS trees, and interconnect lines with 2.4V swings.
Key concepts: NMOS logic, PMOS logic, CMOS, Logic gate, Cascode, AND-OR-Invert, Pass transistor logic, Electrical engineering