2003Unpublished venueRequires access

Development of a tool-set for remote and partial reconfiguration of FPGAs

F. Gehm Moraes, D. Mesquita, Jose Carlos S. Palma, L. Moller, Ney Calazans

Open publisher page 3 citations

Abstract

This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. The main goal is to present a set of tools for remote and partial reconfiguration developed for the Virtex FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGAs.

About this research paper

What this paper is about

This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. The main goal is to present a set of tools for remote and partial reconfiguration developed for the Virtex FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGAs.

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OpenAlex reports 3 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This work describes the implementation of digital reconfigurable systems (DRS) using commercial FPGA devices. The main goal is to present a set of tools for remote and partial reconfiguration developed for the Virtex FPGA family. Even though the tools are targeted to a specific device, their building principles may easily be adapted to other FPGA families, if they have an internal architecture enabling partial reconfiguration. The main contribution of the paper is the tool-set proposed to manipulate cores using partial reconfiguration in existing FPGAs.

Key concepts: Control reconfiguration, Field-programmable gate array, Computer science, Virtex, Embedded system, Set (abstract data type), Computer architecture, Programming language

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