High rate soft output Viterbi decoder
E. Luthi, E. Casseau
Abstract
E. Luthi, E. Casseau
Abstract
This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s, 8 states, R=1/2), using the "radix" trellis method to speed up the rate of a decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of "turbo-codes", which are a class of convolutional codes whose performances in terms of bit error rate, are close to the Shannon limit.
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This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s, 8 states, R=1/2), using the "radix" trellis method to speed up the rate of a decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of "turbo-codes", which are a class of convolutional codes whose performances in terms of bit error rate, are close to the Shannon limit.
Key concepts: Viterbi decoder, Soft output Viterbi algorithm, Convolutional code, Soft-decision decoder, Viterbi algorithm, Iterative Viterbi decoding, Computer science, Turbo code