Liang Zhou, Scott C. Smith
Abstract
This paper develops a new high-speed architecture for asynchronous multiply and accumulate (MAC) feedback circuitry, resulting in a speedup of 1.72 over the previous fastest 72+32times32 asynchronous MAC in the literature.
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This paper develops a new high-speed architecture for asynchronous multiply and accumulate (MAC) feedback circuitry, resulting in a speedup of 1.72 over the previous fastest 72+32times32 asynchronous MAC in the literature.
Key concepts: Speedup, Asynchronous communication, Computer science, Parallel computing, Word (group theory), Computer network, Mathematics, Geometry