Dynamic Power Analysis of Standard-Cell FPGA Fabrics

Synthesizable FPGA fabrics offer several advantages over the full-custom FPGAs produced by the leading commercial FPGA vendors, including process portability and ease of customization to a particular application. In this work, we consider the dynamic power consumption of standard-cell synthesizable FPGAs and quantify the "gap" in power between a synthesized FPGA and its full-custom equivalent. An Intel Stratix-IV-like FPGA, targetable by the VTR flow [9], is implemented in 45nm standard cells using an ASIC toolflow. Post-layout RC extraction is performed, permitting an accurate delay-based simulation for a set of application benchmarks, and detailed power analysis using PrimeTime PX (PTPX). Power results are compared with the same benchmarks implemented on the commercial Stratix-IV (40nm technology). Results show that glitches are a more significant component of power in the standard-cell vs. full-custom FPGA, and that for sequential circuits, the dynamic power gap ranges from 1.3-3.3×.