M.K. Mayes, S.W. Chin
Abstract
A full chip mixed-signal simulation method has been presented. An all Verilog simulation engine verified a 16-bit pipe-lined ADC design for functionality and noise performance. Fast simulation times and high accuracy were achieved using Verilog models for analog components and noise.
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A full chip mixed-signal simulation method has been presented. An all Verilog simulation engine verified a 16-bit pipe-lined ADC design for functionality and noise performance. Fast simulation times and high accuracy were achieved using Verilog models for analog components and noise.
Key concepts: Verilog, Computer science, Mixed-signal integrated circuit, Noise (video), Behavioral modeling, SIGNAL (programming language), Electronic engineering, Simulation