Test generation for acyclic sequential circuits with single stuck-at fault combinational ATPG
H. Ichihara, T. Inoue
Abstract
H. Ichihara, T. Inoue
Abstract
An existing test generation method with a time-expansion model can achieve high fault efficiency for acyclic sequential circuits. While this model is a combinational circuit, a single stuck-at fault in the original circuit is represented by a multiple one in this model. This paper proposes a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in a time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just a combinational test pattern generation algorithm for single stuck-at faults.
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An existing test generation method with a time-expansion model can achieve high fault efficiency for acyclic sequential circuits. While this model is a combinational circuit, a single stuck-at fault in the original circuit is represented by a multiple one in this model. This paper proposes a test generation method for acyclic sequential circuits with a circuit model, called MS-model, which can express multiple stuck-at faults in a time-expansion model as single stuck-at faults. Our procedure can generate test sequences for acyclic sequential circuits with just a combinational test pattern generation algorithm for single stuck-at faults.
Key concepts: Automatic test pattern generation, Combinational logic, Sequential logic, Computer science, Algorithm, Stuck-at fault, Fault coverage, Electronic circuit