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2022•2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT)Requires access

Design of Efficient Pruning Architecture for FFT Algorithm

Chippy Joseph, Sidharth S Prakash

Open publisher page 4 citations

Abstract

Fast Fourier Transform (FFT) is a Digital Signal Processing (DSP) technique to compute Discrete Fourier Transform (DFT) in a faster way by utilizing the properties of the twiddle factor. Conventional FFT has a problem of computational inefficiency when the number of zero valued inputs out-numbers the number of non-zero valued inputs. This is because of the redundant computations on the zero valued inputs. This issue can be resolved by using a technique called pruning in FFT. In this paper we propose an efficient algorithm to reduce the redundant computations in FFT which improves the speed and reduces the power consumption. The proposed algorithm is implemented using verilog HDL.

About this research paper

What this paper is about

Fast Fourier Transform (FFT) is a Digital Signal Processing (DSP) technique to compute Discrete Fourier Transform (DFT) in a faster way by utilizing the properties of the twiddle factor. Conventional FFT has a problem of computational inefficiency when the number of zero valued inputs out-numbers the number of non-zero valued inputs. This is because of the redundant computations on the zero valued inputs. This issue can be resolved by using a technique called pruning in FFT. In this paper we propose an efficient algorithm to reduce the redundant computations in FFT which improves the speed and reduces the power consumption. The proposed algorithm is implemented using verilog HDL.

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OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

Fast Fourier Transform (FFT) is a Digital Signal Processing (DSP) technique to compute Discrete Fourier Transform (DFT) in a faster way by utilizing the properties of the twiddle factor. Conventional FFT has a problem of computational inefficiency when the number of zero valued inputs out-numbers the number of non-zero valued inputs. This is because of the redundant computations on the zero valued inputs. This issue can be resolved by using a technique called pruning in FFT. In this paper we propose an efficient algorithm to reduce the redundant computations in FFT which improves the speed and reduces the power consumption. The proposed algorithm is implemented using verilog HDL.

Key concepts: Twiddle factor, Fast Fourier transform, Split-radix FFT algorithm, Prime-factor FFT algorithm, Computer science, Rader's FFT algorithm, Digital signal processing, Algorithm

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