Design of a core router using the SoCBUS on-chip network

The evolving technology has over the past decade contributed to a bandwidth explosion on the Internet. This makes it interesting to look at the development of the workhorses of the Internet, the core routers. The main objective of this project is to develop a 16 port gigabit core router architecture using intellectual property (IP) blocks and a SoCBUS on-chip interconnection network. The router architecture will be evaluated by making simulations using the SoCBUS simulation environment. Some changes will be made to the current simulator to make the simulations of the core router more realistic. By studying the SoCBUS network load the bottlenecks of the architecture can be found. Changes to the router design and SoCBUS architecture will be made in order to boost the performance of the router. The router developed in this project can under normal traffic conditions handle a throughput of 16x10Gbit/s without dropping packets. This core router is good enough to compete with the top of the line single-chip core routers on the market today. The advantage of this architecture compared to others is that it is very flexible when it comes too adding new functionality. The general on-chip network also reduces the design time of this system.