Design and Analysis of Noise Immune High Speed and Leakage-Tolerant Schmitt Trigger using 180nm CMOS Technology

This paper presents design and analysis of a noise-robust, low-power and high-speed Schmitt trigger circuit. The Proposed Schmitt trigger circuit uses a clock signal for its functionality along with this a PMOS keeper is used to provide a feedback path. Proposed and conventional Schmitt trigger circuits are designed by Cadence Virtuoso software in 180nm CMOS technology and simulated at supply voltage 1.8V. Performance of the proposed Schmitt trigger has been compared with the conventional 6T Schmitt trigger in terms of leakage power consumption, propagation delay, hysteresis width, and power delay product (PDP) as the figure of merit. Simulation result of the Proposed Schmitt trigger circuit provides high speed by efficiently lowering the propagation delay, mitigating static or leakage power by 4x and increasing the hysteresis width by approximately 12.9% when it is compared with conventional 6T Schmitt trigger.