Hardware Circuit Design and Implementation of Digital IF Receiver

Abstract At present, most of the digital IF receivers have bottlenecks in the acquisition and analysis of ultra-high frequency bandwidth signals. At the same time, they have the disadvantages of low resolution and low input bandwidth, which cannot meet the needs of ultra-high frequency signal measurement. In this paper, a high-resolution, high-bandwidth digital IF receiver hardware system is designed based on ADC + FPGA architecture. The front-end analog signal is discretized by two high-speed ADC chips and sent to FPGA to decode the sampling data, and the FFT IP core is called to calculate the power spectrum of the signal. The spectrum data are sent to the host computer through RS485 module and Ethernet chip to display the spectrum image of the original signal in real time, so as to analyze the temperature profile of the target atmosphere.