2016International Journal on Recent and Innovation Trends in Computing and CommunicationOpen access

Analysis and Comparison of Different Multiplier

Jasbir Kaur, Sumit Kumar

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Abstract

Multiplication is one of the important parameter in various digital applications such as in digital signal processor, microprocessor so in this paper firstly we analyse various 4*4 multiplier circuit and then analyses various 12*12 bit multiplier circuit. After then their parameters i.e area, power and delay are analyzed. All these multiplier are designed in Verilog language and synthesized on Xilinx ISE simulator and using cadence RTL schematic respectively. Multipliers included in this paper are Array multiplier, Radix-4 multiplier, Radix-8 multiplier, Wallace Multiplier and Conventional multiplier. On comparison it is found that for 4*4 and 12*12 multiplier, array multiplier have highest delay but have less power consumption while Booth multiplier(Radix-4) is having high speed with moderate power consumption.

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What this paper is about

Multiplication is one of the important parameter in various digital applications such as in digital signal processor, microprocessor so in this paper firstly we analyse various 4*4 multiplier circuit and then analyses various 12*12 bit multiplier circuit. After then their parameters i.e area, power and delay are analyzed. All these multiplier are designed in Verilog language and synthesized on Xilinx ISE simulator and using cadence RTL schematic respectively. Multipliers included in this paper are Array multiplier, Radix-4 multiplier, Radix-8 multiplier, Wallace Multiplier and Conventional multiplier. On comparison it is found that for 4*4 and 12*12 multiplier, array multiplier have highest delay but have less power consumption while Booth multiplier(Radix-4) is having high speed with moderate power consumption.

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Available abstract

Multiplication is one of the important parameter in various digital applications such as in digital signal processor, microprocessor so in this paper firstly we analyse various 4*4 multiplier circuit and then analyses various 12*12 bit multiplier circuit. After then their parameters i.e area, power and delay are analyzed. All these multiplier are designed in Verilog language and synthesized on Xilinx ISE simulator and using cadence RTL schematic respectively. Multipliers included in this paper are Array multiplier, Radix-4 multiplier, Radix-8 multiplier, Wallace Multiplier and Conventional multiplier. On comparison it is found that for 4*4 and 12*12 multiplier, array multiplier have highest delay but have less power consumption while Booth multiplier(Radix-4) is having high speed with moderate power consumption.

Key concepts: Multiplier (economics), Schematic, Verilog, Cadence, Booth's multiplication algorithm, Adder, Arithmetic, Power consumption

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