A high-precision and 10 bit two-step Time-to-Digital Converter for TOF application
YE Xuefeng, Lizhen Tang, Yang Wang, Xiangliang Jin, Yan Peng, Jun Luo
Abstract
YE Xuefeng, Lizhen Tang, Yang Wang, Xiangliang Jin, Yan Peng, Jun Luo
Abstract
A two-step high-precision Time-to-Digital Converter(TDC), integrated with a Single-Photon Avalanche Diode(SPAD), used for Time-Of-Flight(TOF) application, has been developed and tested. Time interval measurement is performed by the coarse counter and fine interpolator, which are utilized to measure the total periods and the residue time of the reference clock, respectively. Following a detail analysis of time precision and clock jitter in the two-step structure, the prototype TDC fabricated in GSMC 1P6M 0.18 µm CMOS Image Sensor(CIS) technology exhibits a Single-Shot Precision(SSP) of 11.415 ps and a dynamic range of 216.7 ns. In addition, a pixel of the chip occupies 100 μm×100 μm, and the measured Integral Nonlinearity(INL) and Differential Nonlinearity(DNL) are better than ±0.88 LSB and ±0.67 LSB, respectively. Meanwhile, the overall power consumption of the chip is 35 mW at 1.8 V power supply. Combined with these characteristics, the designed chip is suitable for TOF-based ranging applications.
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A two-step high-precision Time-to-Digital Converter(TDC), integrated with a Single-Photon Avalanche Diode(SPAD), used for Time-Of-Flight(TOF) application, has been developed and tested. Time interval measurement is performed by the coarse counter and fine interpolator, which are utilized to measure the total periods and the residue time of the reference clock, respectively. Following a detail analysis of time precision and clock jitter in the two-step structure, the prototype TDC fabricated in GSMC 1P6M 0.18 µm CMOS Image Sensor(CIS) technology exhibits a Single-Shot Precision(SSP) of 11.415 ps and a dynamic range of 216.7 ns. In addition, a pixel of the chip occupies 100 μm×100 μm, and the measured Integral Nonlinearity(INL) and Differential Nonlinearity(DNL) are better than ±0.88 LSB and ±0.67 LSB, respectively. Meanwhile, the overall power consumption of the chip is 35 mW at 1.8 V power supply. Combined with these characteristics, the designed chip is suitable for TOF-based ranging applications.
Key concepts: Differential nonlinearity, Time-to-digital converter, Integral nonlinearity, Jitter, Chip, CMOS, Least significant bit, Ranging