Fan-out of 2 Triangle Shape Spin Wave Logic Gates
Abdulqader Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotöfană, Florin Ciubotaru, Said Hamdioui
Abstract
Abdulqader Mahmoud, Christoph Adelmann, Frederic Vanderveken, Sorin Cotöfană, Florin Ciubotaru, Said Hamdioui
Abstract
Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave, and 16 nm and 7 nm CMOS logic gates. The results demonstrate that the proposed structures provide energy reduction of 25%–50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction of 43x-0.8x when compared to the 16 nm and 7 nm CMOS counterparts while having delay overhead of 11x-40x.
OpenAlex reports 4 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
Having multi-output logic gates saves much energy because the same structure can be used to feed multiple inputs of next stage gates simultaneously. This paper proposes novel triangle shape fanout of 2 spin wave Majority and XOR gates; the Majority gate is achieved by phase detection, whereas the XOR gate is achieved by threshold detection. The proposed logic gates are validated by means of micromagnetic simulations. Furthermore, the energy and delay are estimated for the proposed structures and compared with the state-of-the-art spin wave, and 16 nm and 7 nm CMOS logic gates. The results demonstrate that the proposed structures provide energy reduction of 25%–50% in comparison to the other 2-output spin-wave devices while having the same delay, and energy reduction of 43x-0.8x when compared to the 16 nm and 7 nm CMOS counterparts while having delay overhead of 11x-40x.
Key concepts: XOR gate, AND-OR-Invert, Logic gate, CMOS, Pass transistor logic, Energy (signal processing), Overhead (engineering), AND gate