An Academic Framework for IC Physical Design Algorithms Development

Analyzing electronic design automation (EDA) computer aided design (CAD) contests it can be seen that the dominant part of tasks and problems belongs to physical design. This is due to the increments of the complexity of semiconductor devices that discovers an increasing number of new problems to be solved in nanometer scale layouts. As the number of the tasks and their complexity grows the new EDA tools should enhanced to solve the main algorithmic tasks. In this paper we present a new extensible EDA framework for physical level design algorithms development, testing and implementation. The framework provides ready-made solutions for secondary, auxiliary tasks such as file I/O and layout data manipulation. Developed EDA framework was integrated in educational process and made it possible to develop physical design algorithms using technological files. The reported study was done with a support of the state assignment of MIET (Theme No. FSMR-2020-0017/AAAA-A20-120071490038-5).