An Efficient Approach to Tolerate Soft Errors in Combinational Circuits

In recent years, soft errors occur in the combinational logic circuits that seriously influence the activity of digital systems. Thus, the soft error has become a matter of great concern for reliability issues at present. To increase the soft error tolerance, this paper proposes a new method that will reduce the failure rate of the combinational circuits. A method has been introduced which will find out the most common minterms of Boolean algebra. And these minterms are covered by different cubes to maximize the logical masking probability, which reduces the failure rate of a combinational circuit. The experimental study shows how the likelihood of circuit failure is decreased for a given combinational circuit.