Implementation and Analysis of Couple Suppress Current Sense Amplifier at 45nm and 65nm Regime

In this paper, current-sense amplifiers have been implemented and analysed in terms of their delay and power at different corners. The basics of the current sense amplifier and voltage sense amplifier are also discussed. In the result section, the output waveform of the implemented sense amplifier has been included. CMOS layouts of the traditional and coupling suppress modified sense amplifier have been presented and their sensing delay and power are calculated. The gate current of traditional and coupling suppress modified sense amplifiers have also been discussed.