Logic rectification and synthesis for engineering change

In the process of VLSI design, specifications are often changed. It is desirable that such changes will not lead to a very different design, so that a large part of engineering effort can be preserved. We treat this problem as a combination of multiple-error diagnosis and logic minimization problems. Given a new specification and an existing synthesized logic network, our algorithms modify the existing network minimally such that the new specification can be realized. In this paper, a new algorithm is developed to identify multiple candidate signals simultaneously from the existing network, such that appropriate modifications of these signals can rectify the specification change.