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2020•Unpublished venueRequires access

SPAD FDSOI cell optimization for lower dark count rate achievement

Dylan Issartel, T. Chaves de Albuquerque, R. Clerc, Patrick Pittet, R. Cellier, Dominique Golanski, Andreia Cathelin, Françis Calmon

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Abstract

This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages.

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What this paper is about

This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages.

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Available abstract

This article presents an optimization of Single Photon Avalanche Diodes (SPAD) implemented in CMOS 28nm Fully Depleted Silicon-On- Insulator technology. With the standard process and design rules, first attempt of SPAD cells exhibited high Dark Count Rate (DCR) at low excess voltage, attributed mainly to band-to-band mechanism associated with field-enhanced trap assisted tunneling effects. In this study, we propose the modification of the diode junction profile to increase the breakdown voltage, as well as the modification of the SPAD architecture (Shallow Trench Isolation, STI layout). The obtained results with the optimized SPAD confirm significant lower DCR achievement allowing higher excess bias voltages.

Key concepts: Shallow trench isolation, Quantum tunnelling, Optoelectronics, Breakdown voltage, Diode, Silicon on insulator, Dark current, CMOS

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