VLSI Implementation of Bit/Digit Serial-Parallel Finite Field GF (2m) Multiplier Using Standard Basis

A Finite Field is a field with finitely number of elements. It is also known as Galois field in which the elements can take q different values is referred as GF (q).Finite fields are of great interest in applications like Elliptic Curve Cryptography (ECC), error control and coding. In this paper, we present a simple implementation of finite field GF (2 m ) multiplier. Here the main aim is to enhance the vital factors such as area, time complexity, critical path and power. The proposed design is implemented with the finite field accumulator using x-or gates and T-flip-flops. The previous design is even done so that the comparison of the vital factors can be performed. The multiplier structures are implemented using polynomial basis, which is the standard representation and simulated using Xilinx ISE tool version-12.1 and the comparison is performed using Cadence (CAD) tool