Automated Driving of GaN Chireix Power Amplifier for the Digital Predistortion Linearization

This brief presents the measurement/modeling of a dual-input outphasing Chireix power amplifier (PA) for the analysis of nonlinear and memory effects behavior when excited with modulated signals. Moreover, we formulate a cubic-spline (CS) memory model with a closed-loop for the digital predistortion (DPD) linearization algorithm. An FPGA system has been developed to automate the outphasing angles and their respective asymmetrical incident power levels applied at the Class-F PAs of the Chireix under test. Based on experimental results, the CS model offers a DPD with a normalized mean square error (NMSE) of -21.87 dB, and -52.47 dB for a WCDMA 5-MHz and an LTE-A 10-MHz with -26.84 dB and -43.91 dB in extraction and prediction, respectively. An output power improvement of -43.5 dBc in adjacent channel power ratio (ACPR) with 9.3 dB PAPR yield 50% average efficiency enhance at 2 GHz, is achieved.