Determination of Power Loop Inductance for High-Current PCB-Based Half-Bridge Circuits

Higher power densities, smaller passives, are achieved for power electronic converters by increasing the switching frequency. However, the maximum switching frequency is limited by the transistor switching losses for both hard-switched and soft-switched converter topologies. To reduce the switching energy dissipation a half bridge design with low power loop inductance is required. This paper now presents an unequaled verification method that precisely determines the power loop inductance for PCB-based half-bridge circuits employing industry standard high-current transistor packaging. In such PCB designs, the minimization of power loop inductance is largely constrained by thermal vias required for enhanced heat dissipation. By detailed modeling of the transistor packaging and assembly technology maximum result convergence is achieved between Finite Element Analysis and a dedicated measurement environment. The high level of accuracy is finally used to predict the influence of key design parameters on the power loop inductance value to conclude essential design guidelines.