Implementation of 32 bit parallel adder using XILINX IPCORES A Case Study

The paper aims to target the Xilinx intellectual property (IP) cores and the methodology that allows in the easy way of implementing the IP cores and its functionalities and the interface with the recent Xilinx FPGA’s. The proposed work compares the results obtained with the conventional Xilinx programming and the IP cores which are associated with it. VHDL programming style is used to describe the hardware and its functionality. Keywords: Adder, IP, FPGA, VHDL, Xilinx