A Microcode-based Control Unit for Deep Learning Processors

Heterogeneous computing systems that integrate general-purpose processors with various types of application-specific accelerators are becoming mainstream. However, designing an efficient and flexible instruction set architecture (ISA) for a new accelerator is challenging. In this paper, we design a deep learning processing unit (DPU) as an example in order to explore a microcode-based control unit approach for application-specific accelerators. By removing the conventional ISA-based control logic and directly exposing the necessary control signals of the hardware blocks through a sequencer-based microprogrammed control unit, the functional capability of the accelerator is no longer limited by the ISA. Moreover, the design cycle can be shortened because the control logics are moved from hardware to firmware.