Analysis, Physical Design and Power Optimization of Design Block at Lower Technology Node

The VLSI trend is getting complex day by day, especially the complexity of IC technology. It is very important to have better design approach and power optimization methods with constraint on timing closure and physical verification. The IC's designed today are complex and hence require a good Physical Design optimization and strategies. The methodology used in this paper is top down approach. In this paper, different floorplanning of preplaced cells in the design are used as an approach to analyze in terms of timing, area, leakage power and cell densities which is named as Run1, Run2 and Run3. The various optimizations are approached in each stages of physical design specially to reduce the leakage power. Based on the analysis of utilization factor, cell density, QoR and leakage power report generated before and after optimization, finally conclude that Run1 floorplanning is best among Run2 and Run3, with 13.33% improvement in leakage power, 0.417% improvements in area and cell density is better which avoid congestion while routing.