Reverse Engineering for Xilinx FPGA Chips using ISE Design Tools

SRAM-based field-programmable gate arrays (FPGAs) are used in several industries. However, the SRAM-based FPGA is volatile and requires additional nonvolatile memory to store the netlist information of the circuit outside the FPGA as a bitstream file. When the FPGA is powered, the bitstream file is transferred from the external nonvolatile memory to the FPGA. If the bitstream is corrupted, it will cause a fatal problem in the circuit. The process of converting a bitstream into a file that contains the internal netlist information of the FPGA is called reverse engineering. In this paper, we described the process of reverse engineering with mapping table based on ISE design tools in details. To generate the mapping table, we developed XDL generator and RBT comparator which are operated with the input files, XDL, XDLRC and bitstream files. After that, the bitstream in external memory can be recovered the XDL file using mapping table. The reverse engineering tool with mapping table can be recovered 88% internal circuit compared with original circuit.