Designing SRAM Using CMOS and CNTFET at 32 nm Technology

SRAM is one of the most critical components in memory designing. SRAM has become a major data storage device due to large storage capacity and less time to access. In recent research, some challenges like short channel effect, higher power consumption, and low switching speed occur due to submicron scaling of conventional CMOS and thus degrading the performance of the circuit. In order to overcome these issues, Carbon nanotube field-effect transistors (CNTFET) are considered to be one of the suitable alternatives of conventional CMOS technology. The major advantage of considering CNTFET is due to low power, high mobility, and high carrier velocity for faster switching over CMOS technology. Therefore, the proposed work presents the performance comparison of 6T, 7T, 8T, and 10T SRAM using CNTFET and CMOS-based design at 32 nm technology. Consequently, Stanford library is used for designing SRAM with different chiral index to perform the simulations in HSPICE environment. In the proposed work, a comparative analysis is demonstrated between CMOS and CNTFET at 32nm technology. It is observed that the power consumption of CNTFET is improved by 98% as compared to CMOS. Therefore, using an optimal condition for designing SRAM, the power is analyzed at different voltages for diverse chiral number in order to design 6T, 7T, 8T, and 10T SRAM cell.