A Pseudo-Complementary GaN-Based Gate Driver with Reduced Static Losses

This work presents an approach of a normally-off gate driver with reduced static losses based on a n-channel GaN-on-Si technology. The gate driver uses an additional GaN-based pseudo-complementary FET logic (PCFL) stage, which compensates the lack of complementary transistors by complementary logic signals. With this imitated CMOS behavior, static power losses are significantly reduced compared to a nMOS logic inverter. Simulations show that the addition PCFL buffer stage to a conventional driver stage (two nMOS logic inverter and final push-pull stage) enables an almost 10-fold reduction of static losses, while maintaining switching speed and area requirement. In addition, measurements of a PCFL stage illustrate low static power dissipation of . This buffer stage used in this concept enables gate driver losses of <; 3.3 mW.