Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization

In many scientific computations, Lower-upper (LU) decomposition is an important computing step, as most of the scientific applications are modeled using linear equations Ax=b. The Linear equations are used in our everyday life applications such as profit prediction in the business, income over time, mileage rate calculation. The complexity of data makes difficult to parallelize the LU decomposition. Because parallelization of LU decomposition improves the speed of solving LU factorization and reduces the delay in critical applications range from weather forecasting to power system problems-load flow computation. Field Programmable Gate Array (FPGA) is having more logic resources and parallel computing to speed up the matrix decomposition. In this work an area efficient High Throughput Architecture is designed for Sparse Matrix LU factorization by changing/modifying the computing steps in algorithm. The problem with the KLU algorithm is it occupies more area and the throughput is less when compared with the modified KLU algorithm. The area is reduced by the 10%. The hardware complexity of implementation of sparse LU Factorization on FPGA is 15% less when compared with CPU & GPU [4] and also the computing efficiency i.e., throughput 10% to 12% on GPU&CPU do not reach theoretical computing efficiency (theoretical peak throughput).The hardware efficiency (typically 1 to 4%) of UMFPACK and SuperLU, are very less due to poor utilization of Floating point.