Implementation of Interpolator and Decimator Using System Generator

Decimator and Interpolator structures are the basic building blocks which are used in multi-rate DSP for real-time digital processing applications. The technique of decimation/interpolation involves removing/adding of samples in a signal. For implementing the system, several approaches can be initiated that can be performed using filters such as Cascaded Integrated Comb (CIC), FIR and IIR. Among all the filters, CIC filter is preferred one since CIC filter uses only addition and subtraction unlike FIR which uses multiplication. This paper presents an implementation of decimating and interpolating structure which are designed on MATLAB-Simulink using the Simulink library blocks. The implemented structures were mapped to Xilinx block set and VHDL code was generated using HDL Coder for MIMAS V2 Spartan 6 FPGA Board and performance parameters were analyzed.