An Improved iMemComp OR Gate and its Applications in Logic Circuits

The iMemComp (Intelligent memristive computing) gates are a family of logic gates based on the RRAM (Resistive Random Access Memory) devices. It has potential advantage for the design of high-performance logic circuits, because the iMemComp NAND, AND, NOT, and transmission gates only consume single cycle, respectively. However, the original two-input iMemComp OR gate, which requires three cycles, is a relatively slow gate. It decreases the performance of some logic circuits. This work proposes an improved iMemComp OR gate with only one cycle and three RRAM cells. Both the circuit performance and area consumption of the full-adder and LFSR circuits are improved by the application of the proposed OR gate. Furthermore, we propose a general synthesis method of logic circuits based on the improved logic gate. The synthesis results show that the circuits generated from the proposed synthesis method outperform the previous RRAM based counterparts for most cases of the MCNC benchmark circuits.