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2018•2018 International Conference on Advanced Computation and Telecommunication (ICACAT)Requires access

High Level Synthesis Methodology for Exploring Loop Unrolling Factor and Functional Datapath

Pallabi Sarkar, Mrinal Kanti Naskar, Anirban Sengupta

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Abstract

High level synthesis (HLS) forms the backbone of design process for digital signal processing (DSP) kernels. Further design space exploration (DSE) in HLS is quite challenging. However, DSE process becomes more intricate for control DSP kernels (with loops) due to the involvement of a complex variable affecting design area/power and latency called' loop unrolling factor'. This paper presents a process for exploring loop unrolling factor and functional datapath functional units concurrently using genetic algorithm (GA) that meets the user specified design constraints. Results have been tested on variety of DSP kernels along with the sensitivity analysis of GA. The presented approach has been successfully able to converge on optimal solutions in most cases for the tested DSP kernels.

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What this paper is about

High level synthesis (HLS) forms the backbone of design process for digital signal processing (DSP) kernels. Further design space exploration (DSE) in HLS is quite challenging. However, DSE process becomes more intricate for control DSP kernels (with loops) due to the involvement of a complex variable affecting design area/power and latency called' loop unrolling factor'. This paper presents a process for exploring loop unrolling factor and functional datapath functional units concurrently using genetic algorithm (GA) that meets the user specified design constraints. Results have been tested on variety of DSP kernels along with the sensitivity analysis of GA. The presented approach has been successfully able to converge on optimal solutions in most cases for the tested DSP kernels.

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Available abstract

High level synthesis (HLS) forms the backbone of design process for digital signal processing (DSP) kernels. Further design space exploration (DSE) in HLS is quite challenging. However, DSE process becomes more intricate for control DSP kernels (with loops) due to the involvement of a complex variable affecting design area/power and latency called' loop unrolling factor'. This paper presents a process for exploring loop unrolling factor and functional datapath functional units concurrently using genetic algorithm (GA) that meets the user specified design constraints. Results have been tested on variety of DSP kernels along with the sensitivity analysis of GA. The presented approach has been successfully able to converge on optimal solutions in most cases for the tested DSP kernels.

Key concepts: Loop unrolling, Datapath, Computer science, Digital signal processing, Design space exploration, High-level synthesis, Parallel computing, Factor (programming language)

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