Optimizing an Architecture with Software Pipelining Strategies

The search for better execution performance has revealed many parallelism solutions. Among them, the software pipelining technique is reported in the literature to be very promising when applied to instruction level parallelism in Superscalar and VLIW processing architectures. In this paper, we present modifications in two versions of software pipelining technique implemented natively in a general purpose non-conventional processing architecture. The objective of this proposal is to obtain better performance by exploring instruction level parallelism through this technique in an architecture that already explores task level parallelism. Simulation results show that modifications in one version increase performance by almost 3% and decrease the power consumption in 12%.