Design and Implementation of Cache Coherence Protocol for High-Speed Multiprocessor System

To maintain data consistency between the cache memories in centralized and distributed shared-memory multiprocessor system, particular protocols are used known as cache coherence protocols. The performance of a multi-core computer system is strongly influenced by the type of cache coherence protocol used. In this paper, the snoopy bus cache coherence protocols using 3-state, 4-state and 5-state are designed and implemented using the write-invalidate approach in a shared memory dual processor system. The simulation results show that the MOESI protocol reduces the load misses by 48%, memory latency by 35%, power consumption by 18%, increases the gate count by 34% and improves the execution time by 22%. Thus, the overall performance of the MOESI is better than the MESI and MSI cache coherence protocols in a shared memory dual processor system.