Design and Analysis of Different Delay Lines with Different Performance Parameters

In this article, an analysis of different delay lines (DL) based on CMOS (Complementary  metal–oxide–semiconductor) architecture has been done. Comparison has been made on these  delay lines in terms of propagation delay, power dissipation, area, and power delay product. After the analysis of those performance parameters, the tradeoff has been made for better  performance of delay lines. There are 10 stage tapped delay lines which are used. A process  used for calculation of area is clearly described in this article. A 350 nm technology node is  used for simulation. Simulation is done with T-SPICE tool. Keywords: Power delay product, time to digital convertor, propagation delay, area