FPGA Based Performance Comparison of Different Basic Adder Topologies with Parallel Processing Adder

Adders are an almost requisite element of every modern integrated circuit. As in the current era of increasing digitalization, where everyone works towards miniaturization, three important aspects of design, i.e. area, power and delay, need to be optimally balanced. Since adders are used in many complex digital circuits as a basic component, enhancing digital adder performance would greatly accelerate binary operations within such complex circuits. In binary adders, the speed of activity is constrained when taken in propagating the carry through the adder. The adder topology used in our work includes the comparison between Carry Select adder, Carry Look ahead adder, Carry Increment adder, Ripple carry adder and Brent-kung adder. The work is being carried out using Hardware Description Language (HDL) in the platform Xilinx ISE 14.7.