A 2.9 GHz CMOS Phase-Locked Loop with Improved Ring Oscillator

In this paper, a 2.9 GHz phase-locked loop (PLL) based on a three-stage CMOS ring oscillator is presented. A simplified ring voltage-controlled oscillator is used in the PLL fabricated in 110-nm CMOS technology. The delay cell of the VCO only consists of six transistors and the wide tuning range of the proposed ring VCO is from 1.6 GHz to 7.8 GHz. At 1.2V supply voltage, the PLL consumes 13mW at 2.9 GHz output. The worst-case in-band phase noise of the measured PLL is -98 dBc/Hz while the ring oscillator phase noise is -92 dBc/Hz at 1MHz offset.