An FPGA Implementation of Singular Value Decomposition

In linear algebra, Singular Value Decomposition (SVD) refers to factorization process of real or complex matrices that has many applications in engineering, including signal processing, image processing, robotics, bioinformatics, and so forth. Calculating SVD of a matrix by different algorithms always has been a challenge for engineers due to its complex and time-consuming computation process, so that in many cases its application was limited to non-real time offline designs. In this paper, we surveyed the algorithms for calculating SVD, and implemented a customized hardware structure according to the Jacobi algorithm on the FPGA for real-time computation of SVD of arbitrary matrices. Jacobi algorithm, is selected for implementation because of its high parallel processing potential. cyclic method for selecting four Respective elements of the matrix, and a new method for determining the number of sweeps without the time-consuming norm calculation process, along with engaging CORDIC algorithm for calculating basic trigonometric functions resulted in improvement regarding hardware compared to previous works.