The Simeck Family of Lightweight Block Ciphers.
Gangqiang Yang, Bo Zhu, Valentin Suder, Mark D. Aagaard, Guang Gong
Abstract
Gangqiang Yang, Bo Zhu, Valentin Suder, Mark D. Aagaard, Guang Gong
Abstract
Abstract. Two lightweight block cipher families, Simon and Speck, have been proposed by researchers from the NSA recently. In this paper, we introduce Simeck, a new family of lightweight block ciphers that com-bines the good design components from both Simon and Speck, in order to devise even more compact and efficient block ciphers. For Simeck32/64, we can achieve 505 GEs (before the Place and Route phase) and 549 GEs (after the Place and Route phase), with the power consumption of 0.417 µW in CMOS 130nm ASIC, and 454 GEs (before the Place and Route phase) and 488 GEs (after the Place and Route phase), with the power consumption of 1.292 µW in CMOS 65nm ASIC. Furthermore, all of the instances of Simeck are smaller than the ones of hardware-optimized cipher Simon in terms of area and power consumption in both CMOS 130nm and CMOS 65nm techniques. In addition, we also give the secu-rity evaluation of Simeck with respect to many traditional cryptanalysis methods, including differential attacks, linear attacks, impossible differ-ential attacks, meet-in-the-middle attacks, and slide attacks. Overall, all of the instances of Simeck can satisfy the area, power, and throughput requirements in passive RFID tags.
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Abstract. Two lightweight block cipher families, Simon and Speck, have been proposed by researchers from the NSA recently. In this paper, we introduce Simeck, a new family of lightweight block ciphers that com-bines the good design components from both Simon and Speck, in order to devise even more compact and efficient block ciphers. For Simeck32/64, we can achieve 505 GEs (before the Place and Route phase) and 549 GEs (after the Place and Route phase), with the power consumption of 0.417 µW in CMOS 130nm ASIC, and 454 GEs (before the Place and Route phase) and 488 GEs (after the Place and Route phase), with the power consumption of 1.292 µW in CMOS 65nm ASIC. Furthermore, all of the instances of Simeck are smaller than the ones of hardware-optimized cipher Simon in terms of area and power consumption in both CMOS 130nm and CMOS 65nm techniques. In addition, we also give the secu-rity evaluation of Simeck with respect to many traditional cryptanalysis methods, including differential attacks, linear attacks, impossible differ-ential attacks, meet-in-the-middle attacks, and slide attacks. Overall, all of the instances of Simeck can satisfy the area, power, and throughput requirements in passive RFID tags.
Key concepts: Block cipher, Computer science, Application-specific integrated circuit, Cipher, CMOS, Block (permutation group theory), Power consumption, Power analysis