Modeling of Threshold Voltage for 3D Double Gate Fully Depleted SOI MOSFET

With regular scale down of semiconductor devices continuously, when it reached in nanometer regime, threshold voltage changes because of SCE. Back gate voltage plays a significant role for controlling of threshold voltage in such cases. In this paper three dimensional mathematical modeling of threshold voltage is presented, the 3D poisson's equation is solved by using separation of variable method, analytically with suitable boundary conditions for DG SOI MOSFET with the influence of biasing with back gate. In this work, changes in threshold voltage has been demonstrated with respect to channel length considering back and front gate oxide thickness, Drain to source voltages and how short channel effects can be suppressed with application of Back Gate bias voltage.